This paper presents a novel pulsewidth modulation (PWM) strategy for n-level three-leg semiconductor-clamped dc-ac converters in the overmodulation region, with dc-link capacitor voltage balance in every switching cycle. The strategy is based on the virtual-vector concept. Suitable reference vector trajectories are selected to obtain low weighted total harmonic distortion and a simple algorithm. A hexagonal-boundary compression factor is introduced to guarantee, at any operating point, dc-link capacitor voltage regulation capabilities in every switching cycle and avoid narrow gate pulses. The detailed PWM algorithm for an easy implementation in a digital control platform is also presented. The good performance of the strategy is verified through both simulation and experiments in a three-level three-phase neutral-point clamped converter.
- Capacitor voltage balance
- diode-clamped multilevel dc-ac converter
- space vector pulsewidth modulation (SVM)
- three-level neutral-point-clamped converter
- virtual vectors