Implementation of 3L DPWM Techniques for Parallel Interleaved 2L VSIs

Kapil Shukla*, Ramkrishan Maheshwari

*Corresponding author for this work

Research output: Contribution to journalJournal articleResearchpeer-review

Abstract

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal.

Original languageEnglish
JournalIEEE Transactions on Industry Applications
Volume55
Issue number6
Pages (from-to)7604-7613
ISSN0093-9994
DOIs
Publication statusPublished - 1. Nov 2019
Externally publishedYes

Keywords

  • Interleaving
  • pulsewidth modulation (PWM)
  • three-level (3L)
  • two-level (2L)

Fingerprint Dive into the research topics of 'Implementation of 3L DPWM Techniques for Parallel Interleaved 2L VSIs'. Together they form a unique fingerprint.

  • Cite this