Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method during Inductors Mismatch Condition

Kapil Shukla; Ramkrishan Maheshwari

doi:10.1109/TIA.2020.3006464

Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method during Inductors Mismatch Condition

Kapil Shukla^*
, Ramkrishan Maheshwari

^*Corresponding author for this work

Malaviya National Institute of Technology

Research output: Contribution to journal › Journal article › Research › peer-review

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Abstract

Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.

Original language	English
Article number	9133297
Journal	IEEE Transactions on Industry Applications
Volume	57
Issue number	3
Pages (from-to)	3143-3153
ISSN	0093-9994
DOIs	https://doi.org/10.1109/TIA.2020.3006464
Publication status	Published - May 2021

Funding

Manuscript received February 14, 2020; revised June 23, 2020; accepted June 28, 2020. Date of publication July 3, 2020; date of current version May 19, 2021. Paper 2020-MCRE-0338.R1, approved for publication in the IEEE TRANSAC-TION ON INDUSTRY APPLICATIONS by Multilevel Converter applications in the area of Renewable Energy, More Electric Propulsion, Electric Vehicles and Power Grid integration of the IEEE Industry Application Society. This work was supported in part by the IE-Industrial Elektronik project (SFD-17-0036) which has received EU co-financing from the European Social Fund and in part by the Ministry of Electronics and Information Technology (Meity), Government of India. (Corresponding author: Kapil Shukla.).

Keywords

Circulating current
interleaving
pulsewidth modulation (PWM)
voltage source inverter (VSI)

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10.1109/TIA.2020.3006464

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title = "Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method during Inductors Mismatch Condition",

abstract = "Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset. ",

keywords = "Circulating current, interleaving, pulsewidth modulation (PWM), voltage source inverter (VSI)",

author = "Kapil Shukla and Ramkrishan Maheshwari",

note = "Funding Information: Manuscript received February 14, 2020; revised June 23, 2020; accepted June 28, 2020. Date of publication July 3, 2020; date of current version May 19, 2021. Paper 2020-MCRE-0338.R1, approved for publication in the IEEE TRANSAC-TION ON INDUSTRY APPLICATIONS by Multilevel Converter applications in the area of Renewable Energy, More Electric Propulsion, Electric Vehicles and Power Grid integration of the IEEE Industry Application Society. This work was supported in part by the IE-Industrial Elektronik project (SFD-17-0036) which has received EU co-financing from the European Social Fund and in part by the Ministry of Electronics and Information Technology (Meity), Government of India. (Corresponding author: Kapil Shukla.). Publisher Copyright: {\textcopyright} 1972-2012 IEEE.",

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T1 - Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method during Inductors Mismatch Condition

AU - Shukla, Kapil

AU - Maheshwari, Ramkrishan

N1 - Funding Information: Manuscript received February 14, 2020; revised June 23, 2020; accepted June 28, 2020. Date of publication July 3, 2020; date of current version May 19, 2021. Paper 2020-MCRE-0338.R1, approved for publication in the IEEE TRANSAC-TION ON INDUSTRY APPLICATIONS by Multilevel Converter applications in the area of Renewable Energy, More Electric Propulsion, Electric Vehicles and Power Grid integration of the IEEE Industry Application Society. This work was supported in part by the IE-Industrial Elektronik project (SFD-17-0036) which has received EU co-financing from the European Social Fund and in part by the Ministry of Electronics and Information Technology (Meity), Government of India. (Corresponding author: Kapil Shukla.). Publisher Copyright: © 1972-2012 IEEE.

PY - 2021/5

Y1 - 2021/5

N2 - Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.

AB - Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, a significance reduction in the grid side voltage and current ripple could be achieved. However, the parallel interleaved VSIs have a major issue of circulating current. The circulating current is mainly composed of two frequency components: high frequency component and low frequency component. The high frequency component is generated due to the instantaneous difference in the common-mode (CM) voltages of the VSIs. While due to inductance value mismatch in the ac side line frequency inductors, a low frequency circulating current also flows in the system. This low frequency component needs to be controlled as it could saturate the CM, coupled, or interphase inductors used for limiting the high frequency component of circulating current. In this article, an analysis is carried out for circulating current during the inductors mismatch condition. A CM offset signal is also proposed to limit the flow of low frequency component of the circulating current. The proposed CM offset is derived in terms of existing CM offset signals, and hence any existing pulsewidth modulation technique could be implemented using the proposed method. Simulation and experimental results show the improvement in the circulating current using the proposed modified offset.

KW - Circulating current

KW - interleaving

KW - pulsewidth modulation (PWM)

KW - voltage source inverter (VSI)

U2 - 10.1109/TIA.2020.3006464

DO - 10.1109/TIA.2020.3006464

M3 - Journal article

AN - SCOPUS:85106861120

SN - 0093-9994

VL - 57

SP - 3143

EP - 3153

JO - IEEE Transactions on Industry Applications

JF - IEEE Transactions on Industry Applications

IS - 3

M1 - 9133297

ER -

Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method during Inductors Mismatch Condition

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