An Agile Design Methodology using Autobot for Hardware-based Neural Networks

Nan-Sheng Huang

Research output: ThesisPh.D. thesis


Machine learning and artificial intelligence have made significant progress in
many fields, becoming indispensable technologies with potential in a wide
range of applications. Neural networks (NNs) are one of the most promising
machine learning models. However, it is well-known that NN algorithms
feature high computational complexity, being extremely computationally
intensive due to the use of rich synapse connections and neuron models.
For example, the basic computational behavior of a multi-layer perception
(MLP) is the multiply–accumulate (MAC) operation. For image processing
applications, millions of MAC operations per frame are typically required.
For a spiking neural network, the neuron model is based on an ordinary
differential equation, which is even more computationally intensive than that
in the MLP.
For real-time embedded computing on portable edge devices, low power
use and fast execution times are critical design metrics. Central processing
units (CPUs) and graphics processing units (GPUs) are the most popular
computing technologies, due to the relative ease of software programming.
However, higher power consumption and non-real-time operations become sig-
nificant drawbacks when considering portable edge devices. Thus, specialized
hardware accelerator design techniques for field-programmable gate arrays
(FPGAs) or application-specific integrated circuits (ASICs) have been widely
used for real-time and low-power computing. For instance, a smartphone
IC is typically composed of a variety of hardware accelerators, including
those for the wireless baseband, image processing, graphics processing, neural
network processing, and so on. FPGAs have the additional advantage of
field reconfigurability; thus, a developer can change or upgrade the hardware
accelerator after release. Therefore, they are more flexible in embracing future
changes, when compared to ASICs.
However, digital hardware design requires dealing with additional circuit
timing and power closure issues, aside from the correctness of the function.
Logic design with register-transfer level (RTL) using hardware description
languages (HDLs), such as Verilog, VHDL, and SystemVerilog, has become the
mainstream methodology. Although they are capable of controlling the logic
circuit design with finer granularity, the disadvantage of low-level behavior
makes them more challenging to use as easily as software programming
languages. Thus, it always takes longer to complete the hardware design and
it is difficult to change or modify later, compared to when using software
design. In contrast, the emerging high-level synthesis (HLS) methodologies
leverage C/C++ as a design entry, along with the additional hardware-related
synthesis constraints, in order to improve design productivity. However, to
craft a real-time and low-power hardware accelerator using HLS still requires
solid knowledge of computer architectures and logic design, in order to
harness the HLS engine.
From the perspective of machine learning development, the collection of
a correct and complete data set plays a vital role in the success of a model.
Without a good quality data set, network training is in vain. However, it
is inevitable that experiments must be redone in order to collect missing
scenarios or corner cases which were not considered in the initial stage of
new machine learning research. On the other hand, recalibration to retrain a
neural network over time is necessary for proactive BMI control application
in Plan4Act, due to the non-stationary characteristics of neurons in the brain.
When it comes to hardware accelerator design, network retraining may lead
to a change of network topology, requiring the change or redesign of the
hardware. However, it is painful to redesign or modify hardware, due to the
nature of logic circuits.
To mitigate this issue, hardware generation is a powerful methodology on
top of hardware design. Hardware generation facilitates reusability and im-
proves design productivity by wrapping up configurable hardware design. In
this work, we propose using Autobot, a light-weight software agent, to resolve
real-time and low-power hardware generation problems for a class of neural
networks, including MLP, ESN, and RBFNN. Firstly, scalable and configurable
microarchitectures which support floating-point, half-floating point, fixed-
point, and mixed-precision numbers are devised. Then, a template-based HLS
design is adopted to implement the configurable hardware. Next, a basic Auto-
bot is developed to parse, extract the input metadata parameters of the neural
network and golden data set, configure the hardware template and test bench,
and communicate with FPGA development tools for hardware generation.
Furthermore, a smart Autobot with automatic holistic energy-aware design
(AHEAD) methodology is developed to automatically generate the low-power
fixed-point hardware accelerator, in order to eliminate the needs of developers
to conduct fixed-point analysis separately. Furthermore, developers can use
arbitrary machine learning simulation tools and programming languages for
neural network training.
A series of experiments in benchmark problems and proactive BMI con-
trol applications in Plan4Act are conducted to verify the effectiveness of the
proposed methodology. The experimental results show that the proposed
methodology can generate hardware in RTL code in less than 90 seconds
for efficient and rapid design space exploration. Furthermore, the AHEAD
methodology can automatically identify the fixed-point parameters for hard-
ware generation in less than 30 minutes. The iteration time of hardware design
reduces from days or even weeks to only minutes. Thus, the agile hardware
design methodology using Autobot can improve the reusability and design
productivity for real-time and low-power embedded computing.
Original languageEnglish
Awarding Institution
  • University of Southern Denmark
Date of defence10. Nov 2020
Publication statusPublished - 31. Jul 2020


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