A small depth-16 circuit for the AES S-Box

Joan Boyar, Rene Peralta

Research output: Contribution to journalConference articleResearchpeer-review

Abstract

New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].
Original languageEnglish
Book seriesIFIP Advances in Information and Communication Technology
Volume376
Pages (from-to)287-298
Number of pages12
ISSN1868-4238
DOIs
Publication statusPublished - 2012
EventIFIP TC 11 International Information Security and Privacy Conference: Information Security and Privacy Research - Heraklion, Crete, Greece
Duration: 4. Jun 20126. Jun 2012
Conference number: 27

Conference

ConferenceIFIP TC 11 International Information Security and Privacy Conference
Number27
CountryGreece
CityHeraklion, Crete
Period04/06/201206/06/2012

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title = "A small depth-16 circuit for the AES S-Box",
abstract = "New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].",
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A small depth-16 circuit for the AES S-Box. / Boyar, Joan; Peralta, Rene.

In: IFIP Advances in Information and Communication Technology, Vol. 376, 2012, p. 287-298.

Research output: Contribution to journalConference articleResearchpeer-review

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AU - Peralta, Rene

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N2 - New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].

AB - New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].

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KW - circuit

KW - depth

KW - size

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