A small depth-16 circuit for the AES S-Box

Joan Boyar; Rene Peralta

doi:10.1007/978-3-642-30436-1_24

A small depth-16 circuit for the AES S-Box

Joan Boyar, Rene Peralta

Department of Mathematics and Computer Science

National Institute of Standards and Technology

Research output: Contribution to journal › Conference article › Research › peer-review

Abstract

New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].

Original language	English
Book series	IFIP Advances in Information and Communication Technology
Volume	376
Pages (from-to)	287-298
Number of pages	12
ISSN	1868-4238
DOIs	https://doi.org/10.1007/978-3-642-30436-1_24
Publication status	Published - 2012
Event	IFIP TC 11 International Information Security and Privacy Conference: Information Security and Privacy Research - Heraklion, Crete, Greece Duration: 4. Jun 2012 → 6. Jun 2012 Conference number: 27

Conference

Conference	IFIP TC 11 International Information Security and Privacy Conference
Number	27
Country/Territory	Greece
City	Heraklion, Crete
Period	04/06/2012 → 06/06/2012

Documents & Links

10.1007/978-3-642-30436-1_24

https://hal.archives-ouvertes.fr/hal-01518214/document

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1 Organisation or participation in workshops, courses or seminars
1 Talks and presentations in private or public companies

A small depth-16 circuit for the AES S-Box
Boyar, J. (Lecturer)
5. Jun 2012
Activity: Talks and presentations › Talks and presentations in private or public companies
IFIP TC 11 International Information Security and Privacy Conference
Boyar, J. (Participant)
4. Jun 2012 → 6. Jun 2012
Activity: Attending an event › Organisation or participation in workshops, courses or seminars

Cite this

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abstract = "New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].",

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pages = "287--298",

journal = "IFIP Advances in Information and Communication Technology",

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AU - Peralta, Rene

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N2 - New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].

AB - New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].

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KW - circuit

KW - depth

KW - size

U2 - 10.1007/978-3-642-30436-1_24

DO - 10.1007/978-3-642-30436-1_24

M3 - Conference article

SN - 1868-4238

VL - 376

SP - 287

EP - 298

JO - IFIP Advances in Information and Communication Technology

JF - IFIP Advances in Information and Communication Technology

T2 - IFIP TC 11 International Information Security and Privacy Conference

Y2 - 4 June 2012 through 6 June 2012

ER -

A small depth-16 circuit for the AES S-Box

Abstract

Conference

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A small depth-16 circuit for the AES S-Box

IFIP TC 11 International Information Security and Privacy Conference

Cite this