A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple

M. Varun; Kapil Shukla; Ramkrishan Maheshwari; Amit Kumar Jain

doi:10.1109/ICPESYS.2017.8215924

A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple

M. Varun, Kapil Shukla, Ramkrishan Maheshwari, Amit Kumar Jain

Indian Institute of Technology Delhi

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

This paper proposes a new hybrid carrier-based PWM technique for parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) analyzed as a single 3L inverter for line current ripple reduction. The carriers are interleaved to reduce the load side harmonics. However, this allows circulating current to flow between the VSIs. Using the proposed PWM technique, the circulating current is also kept lower than the conventional sinusoidal (SPWM) and space-vector PWM (SVPWM) techniques. Simulation and experimental results justifies the aforementioned statements.

Original language	English
Title of host publication	2017 IEEE 7th International Conference on Power and Energy Systems, ICPES 2017
Number of pages	6
Publisher	IEEE
Publication date	15. Dec 2017
Pages	74-79
ISBN (Electronic)	9781538624289
DOIs	https://doi.org/10.1109/ICPESYS.2017.8215924
Publication status	Published - 15. Dec 2017
Externally published	Yes
Event	7th IEEE International Conference on Power and Energy Systems, ICPES 2017 - Toronto, Canada Duration: 1. Nov 2017 → 3. Nov 2017

Conference

Conference	7th IEEE International Conference on Power and Energy Systems, ICPES 2017
Country/Territory	Canada
City	Toronto
Period	01/11/2017 → 03/11/2017

Keywords

Interleaving
Pulse-width modulation (PWM)
Two-level inverter (2L)
Voltage-source inverter (VSI)

Documents & Links

10.1109/ICPESYS.2017.8215924

Cite this

@inproceedings{11188ba92ecf4ac683435e826fd15391,

title = "A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple",

abstract = "This paper proposes a new hybrid carrier-based PWM technique for parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) analyzed as a single 3L inverter for line current ripple reduction. The carriers are interleaved to reduce the load side harmonics. However, this allows circulating current to flow between the VSIs. Using the proposed PWM technique, the circulating current is also kept lower than the conventional sinusoidal (SPWM) and space-vector PWM (SVPWM) techniques. Simulation and experimental results justifies the aforementioned statements.",

keywords = "Interleaving, Pulse-width modulation (PWM), Two-level inverter (2L), Voltage-source inverter (VSI)",

author = "M. Varun and Kapil Shukla and Ramkrishan Maheshwari and Jain, {Amit Kumar}",

year = "2017",

month = dec,

day = "15",

doi = "10.1109/ICPESYS.2017.8215924",

language = "English",

pages = "74--79",

booktitle = "2017 IEEE 7th International Conference on Power and Energy Systems, ICPES 2017",

publisher = "IEEE",

address = "United States",

note = "7th IEEE International Conference on Power and Energy Systems, ICPES 2017 ; Conference date: 01-11-2017 Through 03-11-2017",

}

Varun, M, Shukla, K, Maheshwari, R & Jain, AK 2017, A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple. in 2017 IEEE 7th International Conference on Power and Energy Systems, ICPES 2017. IEEE, pp. 74-79, 7th IEEE International Conference on Power and Energy Systems, ICPES 2017, Toronto, Canada, 01/11/2017. https://doi.org/10.1109/ICPESYS.2017.8215924

A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple. / Varun, M.; Shukla, Kapil; Maheshwari, Ramkrishan et al.

2017 IEEE 7th International Conference on Power and Energy Systems, ICPES 2017. IEEE, 2017. p. 74-79.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple

AU - Varun, M.

AU - Shukla, Kapil

AU - Maheshwari, Ramkrishan

AU - Jain, Amit Kumar

PY - 2017/12/15

Y1 - 2017/12/15

N2 - This paper proposes a new hybrid carrier-based PWM technique for parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) analyzed as a single 3L inverter for line current ripple reduction. The carriers are interleaved to reduce the load side harmonics. However, this allows circulating current to flow between the VSIs. Using the proposed PWM technique, the circulating current is also kept lower than the conventional sinusoidal (SPWM) and space-vector PWM (SVPWM) techniques. Simulation and experimental results justifies the aforementioned statements.

AB - This paper proposes a new hybrid carrier-based PWM technique for parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) analyzed as a single 3L inverter for line current ripple reduction. The carriers are interleaved to reduce the load side harmonics. However, this allows circulating current to flow between the VSIs. Using the proposed PWM technique, the circulating current is also kept lower than the conventional sinusoidal (SPWM) and space-vector PWM (SVPWM) techniques. Simulation and experimental results justifies the aforementioned statements.

KW - Interleaving

KW - Pulse-width modulation (PWM)

KW - Two-level inverter (2L)

KW - Voltage-source inverter (VSI)

UR - http://www.scopus.com/inward/record.url?scp=85048436052&partnerID=8YFLogxK

U2 - 10.1109/ICPESYS.2017.8215924

DO - 10.1109/ICPESYS.2017.8215924

M3 - Article in proceedings

AN - SCOPUS:85048436052

SP - 74

EP - 79

BT - 2017 IEEE 7th International Conference on Power and Energy Systems, ICPES 2017

PB - IEEE

T2 - 7th IEEE International Conference on Power and Energy Systems, ICPES 2017

Y2 - 1 November 2017 through 3 November 2017

ER -

A new hybrid PWM for two parallel connected interleaved two-level inverter to reduce output current ripple

Abstract

Conference

Keywords

Documents & Links

Other files and links

Fingerprint

Cite this