A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

Lars Baunegaard With Jensen, Anders Kjær-Nielsen, Javier Díaz Alonso, Eduardo Ros, Norbert Krüger

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.
A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.
Original languageEnglish
Title of host publicationReconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Number of pages6
PublisherIEEE
Publication date2008
Pages241-46
ISBN (Print)978-1-4244-3748-1
DOIs
Publication statusPublished - 2008
Event2008 International Conference on ReConFigurable Computing and FPGAs - Cancun, Mexico
Duration: 3. Dec 20085. Dec 2008

Conference

Conference2008 International Conference on ReConFigurable Computing and FPGAs
CountryMexico
CityCancun
Period03/12/200805/12/2008

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Keywords

  • Computer vision
  • FPGA

Cite this

Jensen, L. B. W., Kjær-Nielsen, A., Alonso, J. D., Ros, E., & Krüger, N. (2008). A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. In Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on (pp. 241-46). IEEE. https://doi.org/10.1109/ReConFig.2008.23