Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing

This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.