Resumé
This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.
| Originalsprog | Engelsk |
|---|---|
| Titel | Proceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019 |
| Redaktører | Agata Nawrocka, Andrzej Kot |
| Antal sider | 7 |
| Forlag | IEEE |
| Publikationsdato | 18. jul. 2019 |
| ISBN (Trykt) | 978-1-7281-0703-5 |
| ISBN (Elektronisk) | 9781728107011 |
| DOI | |
| Status | Udgivet - 18. jul. 2019 |
| Begivenhed | 20th International Carpathian Control Conference, ICCC 2019 - Krakow - Wieliczka, Polen Varighed: 26. maj 2019 → 29. maj 2019 |
Konference
| Konference | 20th International Carpathian Control Conference, ICCC 2019 |
|---|---|
| Land | Polen |
| By | Krakow - Wieliczka |
| Periode | 26/05/2019 → 29/05/2019 |
Fingeraftryk
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Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing. / Huang, Nan Sheng; Braun, Jan Matthias; Larsen, Jorgen Christian; Manoonpong, Poramate.
Proceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019. red. / Agata Nawrocka; Andrzej Kot. IEEE, 2019.Publikation: Bidrag til bog/antologi/rapport/konference-proceeding › Konferencebidrag i proceedings › Forskning › peer review
TY - GEN
T1 - Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing
AU - Huang, Nan Sheng
AU - Braun, Jan Matthias
AU - Larsen, Jorgen Christian
AU - Manoonpong, Poramate
PY - 2019/7/18
Y1 - 2019/7/18
N2 - This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.
AB - This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.
KW - Engineering Education
KW - FPGA
KW - Hardware Acceleration
KW - High-Level Synthesis
KW - Intelligent Embedded Systems
KW - Neural Networks
KW - Rapid Prototyping
U2 - 10.1109/CarpathianCC.2019.8765994
DO - 10.1109/CarpathianCC.2019.8765994
M3 - Article in proceedings
SN - 978-1-7281-0703-5
BT - Proceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019
A2 - Nawrocka, Agata
A2 - Kot, Andrzej
PB - IEEE
ER -