Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing

Publikation: Bidrag til bog/antologi/rapport/konference-proceedingKonferencebidrag i proceedingsForskningpeer review

Resumé

This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.

OriginalsprogEngelsk
TitelProceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019
RedaktørerAgata Nawrocka, Andrzej Kot
Antal sider7
ForlagIEEE
Publikationsdato18. jul. 2019
ISBN (Trykt)978-1-7281-0703-5
ISBN (Elektronisk)9781728107011
DOI
StatusUdgivet - 18. jul. 2019
Begivenhed20th International Carpathian Control Conference, ICCC 2019 - Krakow - Wieliczka, Polen
Varighed: 26. maj 201929. maj 2019

Konference

Konference20th International Carpathian Control Conference, ICCC 2019
LandPolen
ByKrakow - Wieliczka
Periode26/05/201929/05/2019

Fingeraftryk

Engineering education
Teaching
Neural networks
Hardware
Particle accelerators
Decoding
Systems analysis
Students
High level synthesis

Citer dette

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title = "Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing",
abstract = "This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.",
keywords = "Engineering Education, FPGA, Hardware Acceleration, High-Level Synthesis, Intelligent Embedded Systems, Neural Networks, Rapid Prototyping",
author = "Huang, {Nan Sheng} and Braun, {Jan Matthias} and Larsen, {Jorgen Christian} and Poramate Manoonpong",
year = "2019",
month = "7",
day = "18",
doi = "10.1109/CarpathianCC.2019.8765994",
language = "English",
isbn = "978-1-7281-0703-5",
editor = "Agata Nawrocka and Andrzej Kot",
booktitle = "Proceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019",
publisher = "IEEE",
address = "United States",

}

Huang, NS, Braun, JM, Larsen, JC & Manoonpong, P 2019, Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing. i A Nawrocka & A Kot (red), Proceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019. IEEE, 20th International Carpathian Control Conference, ICCC 2019, Krakow - Wieliczka, Polen, 26/05/2019. https://doi.org/10.1109/CarpathianCC.2019.8765994

Teaching hardware implementation of neural networks using high-level synthesis in less than four hours for engineering education of intelligent embedded computing. / Huang, Nan Sheng; Braun, Jan Matthias; Larsen, Jorgen Christian; Manoonpong, Poramate.

Proceedings of the 2019 20th International Carpathian Control Conference, ICCC 2019. red. / Agata Nawrocka; Andrzej Kot. IEEE, 2019.

Publikation: Bidrag til bog/antologi/rapport/konference-proceedingKonferencebidrag i proceedingsForskningpeer review

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AU - Larsen, Jorgen Christian

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AB - This paper presents the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design and using HLS as hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical.

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KW - FPGA

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