TY - JOUR
T1 - Model-Driven Design of Network Aspects of Distributed Embedded Systems
AU - Ebeid, Emad Samuel Malki
AU - Fummi, Franco
AU - Quaglia, Davide
PY - 2015/4/1
Y1 - 2015/4/1
N2 - Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model.
AB - Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model.
KW - Modeling and analysis of real time and embedded systems (MARTE)
KW - SystemC/transaction level modeling (TLM)
KW - network manipulation
KW - network synthesis
KW - simulation
KW - unified modeling language (UML)
U2 - 10.1109/TCAD.2015.2394395
DO - 10.1109/TCAD.2015.2394395
M3 - Journal article
SN - 0278-0070
VL - 34
SP - 603
EP - 614
JO - I E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems
JF - I E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems
IS - 4
ER -