Implementation of 3L DPWM Techniques for Parallel Interleaved 2L VSIs

Kapil Shukla; Ramkrishan Maheshwari

doi:10.1109/TIA.2019.2913618

Implementation of 3L DPWM Techniques for Parallel Interleaved 2L VSIs

Kapil Shukla^*
, Ramkrishan Maheshwari

^*Kontaktforfatter

Indian Institute of Technology Delhi

Publikation: Bidrag til tidsskrift › Tidsskriftartikel › Forskning › peer review

Abstract

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal.

Originalsprog	Engelsk
Tidsskrift	IEEE Transactions on Industry Applications
Vol/bind	55
Udgave nummer	6
Sider (fra-til)	7604-7613
ISSN	0093-9994
DOI	https://doi.org/10.1109/TIA.2019.2913618
Status	Udgivet - 1. nov. 2019
Udgivet eksternt	Ja

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Manuscript received November 21, 2018; revised January 21, 2019 and March 5, 2019; accepted April 23, 2019. Date of publication April 25, 2019; date of current version November 7, 2019. Paper 2018-HPC-1121.R2, approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the High Performance Power Electronic Converters: Topologies, Control, and Devices of the IEEE Industry Application Society. This work was supported by the Ministry of Electronics and Information Technology (Meity), Government of India. (Corresponding author: Kapil Shukla.) The authors are with the Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi 110016, India (e-mail:, [email protected]; [email protected]).

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title = "Implementation of 3L DPWM Techniques for Parallel Interleaved 2L VSIs",

abstract = "Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal.",

keywords = "Interleaving, pulsewidth modulation (PWM), three-level (3L), two-level (2L)",

author = "Kapil Shukla and Ramkrishan Maheshwari",

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doi = "10.1109/TIA.2019.2913618",

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AU - Shukla, Kapil

AU - Maheshwari, Ramkrishan

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N2 - Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal.

AB - Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal.

KW - Interleaving

KW - pulsewidth modulation (PWM)

KW - three-level (3L)

KW - two-level (2L)

U2 - 10.1109/TIA.2019.2913618

DO - 10.1109/TIA.2019.2913618

M3 - Journal article

AN - SCOPUS:85075434215

SN - 0093-9994

VL - 55

SP - 7604

EP - 7613

JO - IEEE Transactions on Industry Applications

JF - IEEE Transactions on Industry Applications

IS - 6

ER -

Implementation of 3L DPWM Techniques for Parallel Interleaved 2L VSIs

Abstract

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