HDL code generation from UML/MARTE sequence diagrams for verification and synthesis

Design of Embedded Systems is becoming more and more complex in terms of verify that requirements are fulfilled at different design levels. This requires the simulation of the system and the checking of its timing and functional properties. model-driven design and UML give a reasonable solution to cope with such complexity since they have mechanisms to model and verify embedded systems. This paper presents a methodology which starts from UML/MARTE sequence diagrams with timing constraints and the automatic generation of executable SystemC/TLM and VHDL code with checkers from such diagrams. The simulation of the generated model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. Three case studies are used to show the validity of the approach and a less than linear increase of execution time overhead due to time observation and assertion checkers.