Abstract
Parasitic inductances caused by the package of semiconductor devices in power converters, are limiting the switching speed and giving rise to higher switching losses than necessary. In this study a half-bridge planar power module with Silicon Carbide (SiC) MOSFET bare dies was designed and manufactured for ultra-low parasitic inductance. The circuit structure was simulated and the parasitic inductances were extracted from ANSYS-Q3D. The values were then fed into LT-Spice to simulate the electrical behavior of the half-bridge. The experimental and simulation results were compared to each other and were used to adjust and easily extend the simulation model with additional MOSFETs for higher current capability. It was shown that the proposed planar module, with four parallel SiC MOSFETs at each position, is able to switch 600V and 400A during 40 and 17ns with EON and EOFF equal to 3.1 and 1.3mJ, respectively. Moreover, unlike the commercial modules, this design allows double-sided cooling to extract the generated heat from the device, resulting in lower operating temperature.
Originalsprog | Engelsk |
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Titel | 2018 International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018 |
Forlag | IEEE |
Publikationsdato | 22. okt. 2018 |
Sider | 2732-2737 |
ISBN (Trykt) | 9781538641903 |
ISBN (Elektronisk) | 9784886864055 |
DOI | |
Status | Udgivet - 22. okt. 2018 |
Begivenhed | 8th International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018 - Niigata, Japan Varighed: 20. maj 2018 → 24. maj 2018 |
Konference
Konference | 8th International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018 |
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Land/Område | Japan |
By | Niigata |
Periode | 20/05/2018 → 24/05/2018 |
Sponsor | IEEE Industry Applications Society (IAS), IEEE Power Electronics Society (PELS), IEEJ Industry Applications Society (IAS) |