Resumé
A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.
| Originalsprog | Engelsk |
|---|---|
| Titel | Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on |
| Antal sider | 6 |
| Forlag | IEEE |
| Publikationsdato | 2008 |
| Sider | 241-46 |
| ISBN (Trykt) | 978-1-4244-3748-1 |
| DOI | |
| Status | Udgivet - 2008 |
| Begivenhed | 2008 International Conference on ReConFigurable Computing and FPGAs - Cancun, Mexico Varighed: 3. dec. 2008 → 5. dec. 2008 |
Konference
| Konference | 2008 International Conference on ReConFigurable Computing and FPGAs |
|---|---|
| Land | Mexico |
| By | Cancun |
| Periode | 03/12/2008 → 05/12/2008 |
Fingeraftryk
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A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. / Jensen, Lars Baunegaard With; Kjær-Nielsen, Anders; Alonso, Javier Díaz; Ros, Eduardo; Krüger, Norbert.
Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE, 2008. s. 241-46.Publikation: Bidrag til bog/antologi/rapport/konference-proceeding › Konferencebidrag i proceedings › Forskning › peer review
TY - GEN
T1 - A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors
AU - Jensen, Lars Baunegaard With
AU - Kjær-Nielsen, Anders
AU - Alonso, Javier Díaz
AU - Ros, Eduardo
AU - Krüger, Norbert
PY - 2008
Y1 - 2008
N2 - This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.
AB - This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.
KW - Computer vision
KW - FPGA
U2 - 10.1109/ReConFig.2008.23
DO - 10.1109/ReConFig.2008.23
M3 - Article in proceedings
SN - 978-1-4244-3748-1
SP - 241
EP - 246
BT - Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
PB - IEEE
ER -