A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

Lars Baunegaard With Jensen, Anders Kjær-Nielsen, Javier Díaz Alonso, Eduardo Ros, Norbert Krüger

Publikation: Bidrag til bog/antologi/rapport/konference-proceedingKonferencebidrag i proceedingsForskningpeer review

Resumé

This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.
A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.
OriginalsprogEngelsk
TitelReconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Antal sider6
ForlagIEEE
Publikationsdato2008
Sider241-46
ISBN (Trykt)978-1-4244-3748-1
DOI
StatusUdgivet - 2008
Begivenhed2008 International Conference on ReConFigurable Computing and FPGAs - Cancun, Mexico
Varighed: 3. dec. 20085. dec. 2008

Konference

Konference2008 International Conference on ReConFigurable Computing and FPGAs
LandMexico
ByCancun
Periode03/12/200805/12/2008

Fingeraftryk

Field programmable gate arrays (FPGA)
Processing

Citer dette

Jensen, L. B. W., Kjær-Nielsen, A., Alonso, J. D., Ros, E., & Krüger, N. (2008). A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. I Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on (s. 241-46). IEEE. https://doi.org/10.1109/ReConFig.2008.23
Jensen, Lars Baunegaard With ; Kjær-Nielsen, Anders ; Alonso, Javier Díaz ; Ros, Eduardo ; Krüger, Norbert. / A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE, 2008. s. 241-46
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abstract = "This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.",
keywords = "Computer vision, FPGA",
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Jensen, LBW, Kjær-Nielsen, A, Alonso, JD, Ros, E & Krüger, N 2008, A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. i Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE, s. 241-46, 2008 International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, 03/12/2008. https://doi.org/10.1109/ReConFig.2008.23

A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. / Jensen, Lars Baunegaard With; Kjær-Nielsen, Anders; Alonso, Javier Díaz; Ros, Eduardo; Krüger, Norbert.

Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE, 2008. s. 241-46.

Publikation: Bidrag til bog/antologi/rapport/konference-proceedingKonferencebidrag i proceedingsForskningpeer review

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AU - Ros, Eduardo

AU - Krüger, Norbert

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N2 - This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.

AB - This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.

KW - Computer vision

KW - FPGA

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Jensen LBW, Kjær-Nielsen A, Alonso JD, Ros E, Krüger N. A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. I Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE. 2008. s. 241-46 https://doi.org/10.1109/ReConFig.2008.23