A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

Lars Baunegaard With Jensen; Anders Kjær-Nielsen; Javier Díaz Alonso; Eduardo Ros; Norbert Krüger

doi:10.1109/ReConFig.2008.23

A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

Lars Baunegaard With Jensen, Anders Kjær-Nielsen, Javier Díaz Alonso, Eduardo Ros, Norbert Krüger

Publikation: Kapitel i bog/rapport/konference-proceeding › Konferencebidrag i proceedings › Forskning › peer review

Abstrakt

This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.
A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.

Originalsprog	Engelsk
Titel	Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Antal sider	6
Forlag	IEEE
Publikationsdato	2008
Sider	241-46
ISBN (Trykt)	978-1-4244-3748-1
DOI	https://doi.org/10.1109/ReConFig.2008.23
Status	Udgivet - 2008
Begivenhed	2008 International Conference on ReConFigurable Computing and FPGAs - Cancun, Mexico Varighed: 3. dec. 2008 → 5. dec. 2008

Konference

Konference	2008 International Conference on ReConFigurable Computing and FPGAs
Land	Mexico
By	Cancun
Periode	03/12/2008 → 05/12/2008

Dokumenter og links

10.1109/ReConFig.2008.23

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Citationsformater

@inproceedings{27728840db1011dd9908000ea68e967b,

title = "A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors",

abstract = "This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.",

keywords = "Computer vision, FPGA",

author = "Jensen, {Lars Baunegaard With} and Anders Kj{\ae}r-Nielsen and Alonso, {Javier D{\'i}az} and Eduardo Ros and Norbert Kr{\"u}ger",

year = "2008",

doi = "10.1109/ReConFig.2008.23",

language = "English",

isbn = "978-1-4244-3748-1 ",

pages = "241--46",

booktitle = "Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on",

publisher = "IEEE",

address = "United States",

note = "null ; Conference date: 03-12-2008 Through 05-12-2008",

}

Jensen, LBW, Kjær-Nielsen, A, Alonso, JD, Ros, E & Krüger, N 2008, A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. i Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE, s. 241-46, 2008 International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, 03/12/2008. https://doi.org/10.1109/ReConFig.2008.23

A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. / Jensen, Lars Baunegaard With; Kjær-Nielsen, Anders; Alonso, Javier Díaz; Ros, Eduardo; Krüger, Norbert.

Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on . IEEE, 2008. s. 241-46.

Publikation: Kapitel i bog/rapport/konference-proceeding › Konferencebidrag i proceedings › Forskning › peer review

TY - GEN

T1 - A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors

AU - Jensen, Lars Baunegaard With

AU - Kjær-Nielsen, Anders

AU - Alonso, Javier Díaz

AU - Ros, Eduardo

AU - Krüger, Norbert

PY - 2008

Y1 - 2008

N2 - This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.

AB - This paper describes the hybrid architecture developed for speeding up the processing of so-called multi-modal visual primitives which are sparse image descriptors extracted along contours. In the system, the first stages of visual processing are implemented on FPGAs due to their highly parallel nature whereas the higher stages are implemented in a coarse parallel way on a multicore PC.A significant increase in processing speed could be achieved (factor 11.5) as well as in terms of latency (factor 3.3). These factors can be further increased by optimizing the processes implemented on the multicore PC.

KW - Computer vision

KW - FPGA

U2 - 10.1109/ReConFig.2008.23

DO - 10.1109/ReConFig.2008.23

M3 - Article in proceedings

SN - 978-1-4244-3748-1

SP - 241

EP - 246

BT - Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on

PB - IEEE

Y2 - 3 December 2008 through 5 December 2008

ER -